1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, more specifically a manufacturing method for a semiconductor device comprising a step for forming a second layer on the first layer, the second layer having a lower rate of etching than the first layer, a step for carrying out selective etching to a part of the second layer, a step for forming a conductive layer upward of the second layer, and a step for carrying out selective etching to a part of the conductive layer corresponding to the part of the second layer being etched selectively.
2. Description of the Related Art
A programmable logic device (hereinafter referred to as PLD) is known as a large scale integrated circuit capable of programing logic functions by the user(s). The PLD is constructed so as to provide a number of logic circuits ready-to-operate on the chip for the LSI, and the logic circuits are connected to one another through switches capable of programming. A switching element SW shown in FIG. 5A is considered as one of switches for the PLD.
The switching element SW is constructed by connecting both of a transistor TR1 for programming and a transistor TR2 for switching with each other as shown in FIG. 5A. The transistor TR1 for programming is a split gate type electrically programmable read only memory (EPROM). Also, floating gates FG of the transistor TR1 for programming and the transistor TR2 for switching are formed continuously in common with each other. Control gates CG of both the transistor TR1 and the transistor TR2 are formed continuously in common with each other.
Either of information ON or OFF is written in the transistor TR1 by applying appropriate voltages to a terminal ES, a terminal ED and the control gate CG. The transistor TR2 connects or disconnects a wiring L1 and L2 in accordance with the information written in the transistor TR1.
FIG. 5B and 5C are sectional views showing structures of the transistor TR1 for programming and the transistor TR2 for switching respectively. Also, FIG. 6 is a plan view showing planar structure of the switching elements SW, providing four of them continuously.
A part of the manufacturing processes of the switching element SW (sectional views taken on the planes of the line of P1--P1 and that of the line of P2--P2 in FIG. 6) are shown in FIGS. 7A, 7B, 7C and FIGS. 8A, 8B and 8C. In order for manufacturing the switching element SW, a semiconductor-substrate 2 being formed both of a gate oxidation layer 4 and a polysilicon layer 6 is prepared.
Thereafter, a floating gate FG is formed by carrying out anisotropic etching (see FIGS. 7B and 7C) after performing patterning of a resist layer 8 (see FIG. 7A).
Then, an inter layer 12 is formed by oxidizing both the surface of the semiconductor-substrate 2 and the floating gate FG (see FIG. 8A). After forming the inter layer 12, a polysilicon layer 14 is formed. The polysilicon layer is patterned by a resist layer 16 (see FIG. 8B).
Further, a control gate CG is formed by carrying out anisotropic etching by using the resist layer 16 as a mask (see FIG. 8C). Thus, the switching element SW is manufactured.
However, the manufacturing processes of the switching element SW described above have the following problems to be resolved. The floating gate FG is formed by carrying out anisotropic etching to the polysilicon layer 6 (see FIG. 7B) first, and then wet-etching is performed at the final phase (see FIG. 7C).
During the final phase of the etching processes, a silicon oxidation layer for separating the elements formed by the method of a local oxidation of silicon (hereinafter referred to as LOCOS layer 20) is etched at a much higher speed than that of the polysilicon layer 6, because the LOCOS layer 20 has a higher rate of etching than that of the polysilicon layer 6. As a result, as shown in the section P2--P2 of FIG. 7C, the polysilicon layer 6 remains in a shape of eaves on the LOCOS layer 20 thus etched.
Not much of an inter layer 12 is formed on the LOCOS layer 20 when the inter layer 12 is formed by oxidizing both the surface of the semiconductor-substrate 2 and the polysilicon layer 6 (floating gate FG) (see FIG. 8A), because the rate of forming an oxidation layer of the LOCOS layer 20 is lower than that of the polysilicon layer 6.
Consequently, a larger size of the inter layer 12 is formed in a shape of eaves 12a on the LOCOS layer 20 as shown in the section P2--P2 of FIG. 8A.
Therefore, as shown in the section P2--P2 of FIG. 8B, a polysilicon layer 14 is formed so as to get underneath the eaves 12a when the polysilicon layer 14 is accumulated on the inter layer 12.
As a result of that, as shown in the section P2--P2 of FIG. 8C, the polysilicon layer 14 formed underneath the eaves 12a can not be removed completely even when the polysilicon layer 14 formed on the LOCOS layer 20 is removed by anisotropic etching. The polysilicon layer 14 thus remaining underneath the eaves 12a is referred to as stringers 22 (illustrated by chain double dashed line in FIG. 6).
As shown in FIG. 6, both of the control gates CG are connected electrically which must be electrically insulated from each other. So that, the stringers 22 might be a cause of erroneous operation of the switching element SW.